The present invention relates to semiconductor fabrication and more specifically, to perform uplift analysis and optimization of fabricated semiconductor chips.
Very-large-scale integration (VLSI) is a traditional process used to create an integrated circuit (IC) by combining thousands of semiconductor devices (e.g., transistors) into a single semiconductor wafer, i.e., chip. High-performance VLSI design requires a very accurate representation of three-dimensional (3D) parasitic data which is then incorporated into different analysis and optimization tools. For example, 3D parasitic coupling information is used by timing, noise and power analysis, and optimization tools. This parasitic coupling information is useful in design optimization since the existence of parasitic coupling can reduce signal propagation time and introduce noise in a semiconductor network formed on the chip.
Various optimization tools are used to analyze the current state of the design with respect to one or more analysis-criteria perform-changes (ACPCs). The results from the ACPC analysis may be utilized to improve the criteria and re-analyze the state of the design to indicate whether improvement was in fact achieved. Previous approaches, however, either capture only the changes of directly connected components or manage the coupling by continuously re-calculating the Miller-factor (i.e., k-factors) of the design.
The infra-structure to support the analysis of a design change is typically incremental due to the requisite accuracy and turn-around time. In order to satisfy the accuracy and time limitations, incremental on demand parasitic extraction schemes are typically employed in traditional incremental analysis systems to obtain the parasitic information utilized by various analysis and optimization tools. The extracted parasitic information typically includes obtaining capacitance and resistance information between a first net and one or more adjacent nets. However, maintaining the combined parasitic network necessary to conduct incremental on demand parasitic extraction while performing incremental design changes requires complex actions to ensure the combined extracted network is kept up-to-date.